Zero ASIC Releases Wildebeest: The World’s Highest Performance FPGA Synthesis Tool Date & Location: Cambridge, MA – September 17, 2025 Company: Zero ASIC, a semiconductor startup focused on democratizing silicon through chiplets and design automation. --- Background The software industry shifted from proprietary compilers to high-quality open source compilers like LLVM and GCC. A similar transformation is underway in hardware design: Open-source FPGA synthesis tools, such as Yosys (Verilog RTL synthesis) and Slang (SystemVerilog support), now exist due to community efforts. However, open-source tools have lagged behind proprietary solutions in quality of results (QoR) and performance. Industrial users face a trade-off between open freedom and high performance. | Attribute | Vendor Tool | Yosys | |-----------------|-------------|------------| | FPGA Support | Yes | No | | Lock-in | Yes | No | | Open Source | No | Yes | | Free | Yes/No | Yes | | Binary Size | Large | Small | | QoR | Great | Good | | Robustness | Great | Good | --- Wildebeest Introduction Wildebeest brings advanced synthesis optimizations to the open-source world, introducing techniques previously exclusive to proprietary tools: Circuit size-based optimization: Uses different algorithms depending on circuit size to maintain robustness and high performance for designs up to 1 million LUTs. Advanced abc9 commands: Employs ABC synthesis library’s powerful features for speculative synthesis and logic depth minimization. Industrial benchmarking: Developed with 150+ internal benchmarks and automated profiling, complemented by the open-source LogikBench for independent evaluation. Expertise: Developed by industry veteran Dr. Thierry Besson with 30 years in logic synthesis, releasing several advanced techniques to public open source. --- Benchmark Results Wildebeest outperforms both open-source and commercial synthesis tools on the Picorv32 CPU design: | Device | Arch | Tool | Command | LUTs | Logic Depth | |--------|------|------------|--------------------|------|-------------| | z1060 | LUT6 | wildebeest | synthfpga | 2312 | 40 | | z1060 | LUT6 | wildebeest | synthfpga -opt delay | 2677 | 6 | | Vendor-1 | LUT6 | vendor | proprietary | 2870 | 7 | | Vendor-2 | LUT6 | vendor | proprietary | 2947 | 8 | | xc7 | LUT6 | yosys (0.56) | synthxilinx -nocarry | 3072 | 17 | | z1010 | LUT4 | wildebeest | synthfpga | 3593 | 39 | | z1010 | LUT4 | wildebeest | synthfpga -opt delay | 4112 | 8 | | ice40 | LUT4 | yosys (0.56) | synthice40 -dsp -nocarry | 4378 | 33 | Wildebeest shows superior QoR compared to both open source and proprietary tools. --- Future Work Wildebeest’s initial release marks the start of ongoing optimization efforts aiming to significantly surpass current proprietary tools. The long-term vision includes fostering an "LLVM for synthesis" ecosystem: Collaborating with communities Developing high-performance open tools Establishing robust standard IRs and file formats Encouraging broad adoption by hardware vendors --- Demo and Availability Try Wildebeest: Follow installation instructions. Use the example picorv32 CPU design. Sample Yosys command sequence: Source Code: Open source released on