Alibaba Cloud FPGA: The $200 Kintex UltraScale+ Introduction Seeking an FPGA for new projects, the author aimed for Xilinx Kintex UltraScale+ series, specifically the XCKU3P or XCKU5P, supported by the free Vivado WebPack. These are high-end devices with large resources (e.g., 162K+ LUTs, 16 GTY transceivers up to 32.75 Gb/s). Required board features: at least 2 SFP+ or 1 QSFP connectors, JTAG, and PCIe x8. Alternatives were designing a board, buying from Alinx (~$900-1050), or finding second-hand. A second-hand Alibaba Cloud decommissioned FPGA accelerator was found on eBay for $200—no docs, no guarantee, but tempting. The Debugger Challenge Official Xilinx tools are costly and proprietary. Using OpenOCD, an open-source debugger with support for JTAG and SVF files, to program the FPGA. Challenge: OpenOCD support for UltraScale+ FPGAs is limited; no native ILA integration, but basics like configuration via JTAG and SVF are possible. The Plan Incremental steps to turn the board into a usable dev platform: Confirm board functionality: Check for PCIe endpoint or SFP+ ethernet activity using existing bitstream. Connect debugger: Identify and connect to JTAG interface; figure out the JTAG scan chain. Determine pinout: Identify board clocks, PCIe lanes, SFP+ connections. Write bitstream: Develop a workflow using Vivado-generated SVF files and program via OpenOCD and JTAG (no flash rewriting initially). Liveness Test Board arrived with additional Huawei SFP28 transceiver and fiber cable. Minor wear noted; PCIe and transceiver connectors intact. Powered via PCIe-to-USB adapter, with LEDs and FPGA heat indicating power-up. PCIe Interface Connected FPGA board to Raspberry Pi 5 (has PCIe Gen 2.0 x1). Linux dmesg showed: PCI bridge (Broadcom BCM2712) Unknown vendor id device dabc:1017 detected as Ethernet controller → likely FPGA board. lspci -vvv detailed PCIe capabilities: Board supports PCIe Gen3 x8, running downgraded to Gen2 x1 due to Pi's limitations. Confirms working PCIe interface on FPGA board. JTAG Interface Board features a 6-pin accessible JTAG interface (TCK, TMS, TDI, TDO plus power/ground). No standard interface connector; rewiring to Segger JLink + open source OpenOCD is used. JTAG speed lowered to 1 MHz for probing due to wiring; programming at 10 MHz. JTAG Scan Chain OpenOCD auto-probing found one device with IDCODE 0x04a63093 matching Xilinx KU3P FPGA. FPGA IR length is 6 bits (not default 2 bits), requires configuration in OpenOCD. Single TAP device on the chain. System Monitor (SYSMON) UltraScale+ uses SYSMON4 for temperature and voltage monitoring. Added custom OpenOCD support scripts to: Select SYSMON DRP mode (IR=0x37) Read temperature, voltages, and max recorded values via JTAG. Reads found chip temperature ~31°C and voltages within expected values. Pinout and Clocks Found partial undocumented board pinout on external blog ("truck-kun pinout"). Confirmed differential clock pairs: 100MHz clock on pins E18/D18 (global clock input) 156.25MHz clock on K7/K6 as GTY transceiver reference (SFP+ likely) Verified pin properties via Vivado TCL commands. Created constraint file (alibabacloud.xdc) to reflect this pinout. Test Design Simple Verilog top-level using differential 100MHz clock input driving a counter displayed on 4 LEDs. Constraint file maps clock and LEDs to correct pins/banks. Writing the Bitstream Vivado Flow (Automated) Batch mode with TCL scripts and Makefile coordinating: setup.tcl: create Vivado project for KF3P FPGA. build.tcl: synthesize, implement, route design, generate checkpoint. gen.tcl:** write bitstream and export SVF. Makefile automates entire workflow. Generating SVF SVF allows vendor-agnostic JTAG sequences, easy to send with OpenOCD. Vivado hardware manager APIs